(1) Field of the Invention
The present invention relates to frequency multipliers, in general, and to multipliers using solid-state components employing quasi-vertical diode geometry for generating high-frequency millimeter and submillimeter-waves signals, in particular.
(2) Description of Related Art Including Information Disclosed Under 37 CFR §§ 1.97 and 1.98
Frequency multipliers are the most commonly used solid-state components for generating, high-frequency millimeter and submillimeter-wave signals, These components are based on a nonlinear device, typically a Schottky diode, that is driven with a low frequency, high-power source. The nonlinearities of the device produces harmonics of this input, which are subsequently extracted to realize a higher-frequency source. The most common types of frequency multipliers are doublers (which produce power at twice the input frequency) and triplers (which produce power at three times the input frequency). Doublers and triplers are most often realized with multiple-device architectures (such as anti-series or anti-parallel diode arrangements) naturally separate even and odd-order harmonics.
Extending multipliers to higher frequencies is difficult, as it typically requires complex circuits designed to idle power generated at undesired intermediate frequencies. Consequently, most high-order multipliers consist of cascaded chains of doublers and triplers with intermediate “matching” stages designed to optimize the impedance seen by each preceding multiplier stage, Unwanted reflections at these intermediate stages can detrimentally affect the performance of a multiplier driving other multipliers, thus reducing efficiency and bandwidth. Consequently, isolators or other lossy circuits are often used between stages to reduce such loading effects. This reduces the overall efficiency of the chain and places increased demand on the power handling of earlier stages as the entire chain must often be driven with higher levels of power to achieve a given, target output power.
Frequency multipliers based on Schottky barrier diodes represent the most commonly used solid-state device technology for generating power at frequencies ranging from 100 GHz, to 1 THz. Over the years, these devices have remained critical to a variety of submillimeter-wave heterodyne-based instruments including radiometers for space-borne applications, receivers for ground-based radio astronomy, and sources for vector network analyzer frequency extenders. The design of varactor multipliers is well established. From this foundation, a number of preferred multiplier circuit topologies have emerged including balanced doubler and tripler configurations that employ anti-parallel or anti-series connected diodes. These circuit configurations have become commonplace due to their inherent isolation of even-order and odd-order harmonics, eliminating the need for filters.
Generation of power at frequencies approaching 1 THz typically requires many stages of multiplication as the fundamental input signal is often in the microwave range where significant (watt-level) drive power is achievable. Direct multiplication to a high-order harmonic greater than the third is usually not considered practical as proper termination of all intermediate harmonics (idlers) is a complex (and sometimes intractable) design problem. Consequently, submillimeter wave multiplier sources typically consist of a chain of doublers and triplers, selected to yield the desired output frequency. Cascading of multipliers provides a pragmatic approach, with output powers of hundreds of milliwatts being obtained in the millimeter-wave band with this technique. However, because the efficiencies for varactor doublers and triplers operating above 100 GHz are typically no greater that 25%, the overall efficiency of a large multi-stage chain is often substantially lower than 1%. Moreover mismatches between adjacent multipliers in a cascade can readily disturb earlier multiplier stages by pulling them from their optimum operating point, further reducing efficiencies and output power. As a result, intermediate matching or isolation networks are frequently inserted between adjacent stages, contributing to loss and system complexity. Moreover, the input stages of large multiplier chains must be capable of handling high power (several watts) to overcome the low efficiencies and produce usable output power, which is often on the order of 1 μW above 1 THz.